A Divided Decoder-Matrix (DDM) Structure and Its Application to a 8kb GaAs MESFET ROM

This paper describes a new approach which allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix. As an application of the DDM technique, an 8Kbit MESFET ROM has been designed with a standard 0.6 μm-gate MESFET process. The ROM has a typical access time of 1.2 ns and a power dissipation of 60 mW.